Silicon semiconductor devices are now playing the leading part of electronic equipments. But on other hand new material is looked for to further improve the operation speed of the devices. Gallium arsenide (GaAs) is one of such new material which has capability to realize higher operating speed because of its higher electron mobility than that of silicon, and devices using such material is now under development.
As a device utilizing compound semiconductor such as gallium arsenide, field effect transistor (FET) is ahead of development because its fabrication process is simple compared to that of bipolar transistor. Especially schottky barrier type FET whose parasitic capacitance is reduced by using semi-insulating substrate of compound semiconductor is becoming a main stream of the development.
In normal structured semiconductor devices of silicon or gallium arsenide, carriers move through semiconductor lattice space where impurity ions are existing. Motion of the carrier is affected by lattice and impurity ions, and loose is mobility by collision and scattering with them. It is possible to decrease the effect of scattering by lattice (interaction with phonon) by decreasing the temperature, but it increases the scattering by impurity ions so the mobility of the carrier is limited.
In order to sustain the high electron mobility especially in cryogenic temperature by eliminating the effect of ionized impurity scattering, multilayered structure has been proposed (for example U.S. Pat. No. 3,626,257 by Esaki et al.), interleaving layers having different bandgap each other. Such structure intends to separate the layer where the carriers drift (it is called as channel layer) from the layer where impurity is doped to supply the carriers. Such separation is done by heterojunction between the layers, so it is called as selectively doped (or modulation doped) heterojunction FET or high electron mobility transistor (HEMT).
In order to make clear the advantage of the present invention, structure of prior art heterojunction FET, its problems, and some attempts to improve them will be described briefly. FIG. 1 shows two types of prior art heterojunction FETs. In the FIG. 1 is a semi-insulating gallium arsenide (GaAs) substrate, in some cases it is intentionally doped with chromium (Cr) or iron (Fe) etc. to compensate the effect of unintentionally doped impurities, and provide a very high resistivity. On the substrate 1 is piled in order from the surface of the substrate a undoped i-type GaAs layer 2, an aluminum-gallium arsenide (Al.sub.x Ga.sub.1-x As) layer 3 which has smaller electron affinity compared to that of the layer 2, and an n-type GaAs layer 4. The n-type GaAs layer 4 is highly doped to secure a good contact with contact wires and shaped to form source and drain electrodes as shown in the figure. When gate electrode 5, source electrode 6 and drain electrode 7 are fabricated, the heterojunction FET is completed.
In the example of FIG. 1(a), the Al.sub.x Ga.sub.1-x As layer 3 is doped with silicon (Si), for example, and becomes n-type. Carriers (in this case is electron) formed in the doped layer 3 are transferred to the undoped layer 2 and accumulates in the layer 2 near the heterojunction between the i-type GaAs layer 2 and the Al.sub.x Ga.sub.1-x As layer 3, and forms two-dimensional electron gas 2A as shown in the figure. This two-dimensional electron gas (abbreviated as 2DEG) plays a role of channel in FET, and often called as channel layer. When the device is cooled to the cryogenic temperature, the lattice scattering decreases, and since the i-type GaAs layer 2 is not doped and ionized impurity is very rare, the 2DEG is not suffered from the scattering by the ions and it sustains high mobility. Thus high speed operation of the heterojunction FET is attained.
It was found that by the structure of FIG. 1(a) some of the carriers in the 2DEG 2A are affected by the ions in the Al.sub.x Ga.sub.1-x As layer 3, so the mobility of the carrier does not become sufficiently high. So it has been proposed to provide a buffer zone or spacer between the 2DEG and the carrier supplying layer (for example U.S. Pat No. 4,163,237). FIG. 1(b) shows an example of such structure. Compared to FIG. 1(a), the Al.sub.x Ga.sub.1-x As layer 3 is subdivided into two layers 3a and 3b. Contiguous with the i-type GaAs layer 2 is formed a thin layer of undoped Al.sub.x Ga.sub.1-x As layer 3a, which acts as the buffer zone or spacer. Over the buffer zone 3a is formed the carrier supplying layer 3b which is a Si doped layer for example. Thickness of the buffer zone is few tens of .ANG..
Applying such structure for GaAs devices, the mobility of 2DEG exhibited 1.times.10.sup.5 cm.sup.2 /VS at 77.degree. K., with a 2DEG concentration of 6.times.10.sup.11 cm.sup.-2 and the high speed operation of GaAs FET has been improved to a great extent. But there came out another problem. GaAs FET of the above mentioned structure has been fabricated with a process whose temperature is fairly low compared to ordinary semiconductor manufacturing process. For example the source or drain electrode has been fabricated with eutectic ally of gold and gold-germanium (AuGe/Au) whose eutectic temperature is 450.degree. C., and the heating time has been kept to less than one minute. With such care, the thermal diffusion of impurities from the doped Al.sub.x Ga.sub.1-x As layer 3b into the spacer region of undoped Al.sub.x Ga.sub.1-x As layer 3a has been suppressed. If not, the impurity in the layer 3b will diffuse into the spacer layer 3a, and the mobility is decreased by the interaction with the impurity ions.
By the way, recent electron devices are used in complex form with some other devices. Therefore, single FET is almost meaningless though it has very high speed, it must be used together with other devices, it must be weaved into IC or it must compose IC by itself. In order to use a high electron mobility transistor (HEMT) for practical use, therefore, it is necessary to make it strong to bear the process temperature of about 700.degree. C. Such temperature is required for example for driving impurities into semiconductor material by diffusion, or annealing the device to activate the impurities implanted by ion implantation.
One easy way was applying a local heating by energy beam such as infrared ray, electron beam for example, but they were applicable only for limited use. Some attempts has been proposed (for example Japanese laid open patents Provisional Publication Nos. 57-193067, 58-51573, 58-51574 and 58-51575). One attempt was to make thick the spacer layer estimating the diffusion of impurities into the spacer by thermal diffusion, other one was to make additional layer of n-GaAs layer. Though these attempts have their own significances, but it is still insufficient to sustain the high electron mobility bearing high process temperature.
It is the main object of the present invention, therefore, to provide a structure of high electron mobility semiconductor devices which bears a process temperature of more than 700.degree. C.
Another object of the present invention is to provide a high electron mobility transistor (HEMT) which can be used together with other electron devices as an integrated circuit.